CPU Senior Timing Engineer

Intel's CPU design team develops high-performance computing designs. This engineer drives CPU timing analysis and closure, resolves critical timing issues, and improves timing methodology through automation.

• Drive top-level timing analysis and closure for CPU IP
• Develop and maintain timing constraints, MMMC scenarios, and path budgets
• Resolve setup, hold, clock gating, noise, and cross-block timing issues
• Coordinate timing closure with RTL, block, physical design, and clock teams
• Correlate block-level, top-level, and signoff timing environments
• Automate timing analysis and reporting with scripts and methodology improvements

Education

Engineering degree

Degree

electrical engineering, electronics engineering

Experience

3+ years

Domain

semiconductors

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