Staff/ Senior Staff Engineer, STA

Renesas ElectronicsCV Raman Nagar, BangalorePosted 10 days ago

Senior
Full time
7 to 13 years

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About the role

Renesas develops semiconductor products for automotive, industrial, cloud, and IoT applications. This engineer will analyze and close timing for block-level and full-chip designs and support signoff and tapeout.

What you'll do

Perform block-level and full-chip static timing analysis across modes and corners
Develop, validate, and maintain timing constraints and exceptions
Debug timing violations and drive closure through optimization and ECOs
Collaborate with design, synthesis, clock-tree, and physical-design teams
Support pre-layout and post-layout analysis and tapeout signoff
Improve STA methodologies, automation, and timing closure reporting

Skills

Must have

Static timing analysis
Timing closure
Timing constraints
Setup and hold analysis
Path-based analysis
Timing signoff
Ocv
Aocv
Pocv
Mmmc analysis

Nice to have

Low-power timing analysis
Signal integrity analysis
Crosstalk analysis
Ir-drop-aware timing closure
Flow development

Tools

Synopsys primetime
Cadence tempus
Tcl
Perl
Python
Upf
Cpf
Sdc

Who it's for

Education: Engineering degree
Degree: electrical engineering, electronics engineering, vlsi, microelectronics
Experience: 7 to 13 years
Domain: semiconductors