Principal Synthesis, STA Engineer

Analog Devices develops semiconductor technologies that connect the physical and digital worlds. You will lead synthesis, static timing analysis and timing closure for complex high-performance SoCs.

• Lead synthesis and timing closure across IP, subsystem, partition and full-chip levels
• Develop and validate hierarchical timing constraints
• Drive multi-mode, multi-corner timing signoff and closure methodology
• Plan and balance top-level clocks with Physical Design teams
• Root-cause timing and quality-of-results issues across the RTL-to-GDS flow
• Execute timing ECOs for setup, hold and DRC closure

Experience

10 to 15 years

Domain

semiconductors

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