RTL Engineer Memory Subsystem - Bangalore

Velaura is building compute technology for cloud, edge, and Physical AI systems such as robots and autonomous machines. You will design and integrate high-speed, low-power memory subsystem RTL for its SoC.

• Design and optimize RTL for SoC memory controllers and fabric interfaces
• Integrate memory controllers with PHYs, including training and bring-up flows
• Improve memory-path timing, power, bandwidth, and latency
• Define hardware interfaces, memory maps, and performance-critical interactions with software teams
• Analyze memory bottlenecks and propose architectural improvements
• Partner with verification, physical design, and memory IP teams through silicon bring-up

Domain

semiconductors ai hardware

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