ASIC Engineer
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About the role
Cisco SiliconOne develops networking chips for enterprise and service provider solutions. You will implement ASIC physical design from RTL to GDS, optimizing performance and die size while driving timing, power integrity, and verification closure.
What you'll do
- Implement hierarchical floor planning, place and route, and RTL-to-GDS flows
- Drive timing closure and physical convergence for multi-mode, multi-corner designs
- Perform power integrity analysis and physical verification
- Develop automation scripts and physical design methodologies
- Optimize performance and die size for advanced-node networking chips
Skills
Must have
- Asic physical design
- Floor planning
- Place and route
- Timing closure
- Clock and power distribution
- Static timing analysis
- Power integrity analysis
- Physical verification
- Equivalence checking
- Timing eco implementation
Nice to have
- Clock tree synthesis
- Physical design methodology development
Tools
- Primetime
Who it's for
- Education
- Engineering degree
- Degree
- electrical engineering, computer engineering
- Experience
- 8+ years
- Domain
- networking chips
About Cisco
Cisco has 173 open roles in Bangalore, at Cisco Bangalore Campus (Cessna Business Park). See every Cisco role.
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