ASIC VERIFICATION ENGINEER

Broadcom develops switching products for AI network infrastructure. You will build and maintain SystemVerilog/UVM verification environments and verify chip features through coverage closure and simulation.

• Develop and maintain SystemVerilog/UVM verification environments
• Understand end-to-end specifications and network and system topology
• Develop test plans with architecture and design teams
• Close coverage and run gate-level simulations
• Debug hardware-software co-simulation flows

Experience

8+ years

Domain

ai network infrastructure

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