Lead digital verification engineer

NXP’s NVM IP design group develops non-volatile memory IP for multiple business verticals. You will lead pre-silicon verification activities, build UVM verification environments, and validate NVM controller modules.

• Define verification strategies and plans for IP modules
• Develop, debug, and run SystemVerilog UVM verification environments
• Create test cases, stimulus, and assertions for design models
• Run simulations and regressions across RTL and gate-level models
• Analyze code and functional coverage
• Coordinate verification requirements with digital design teams

Education

Engineering degree

Degree

microelectronics, electronics, electrical engineering, computer science

Experience

8+ years

Domain

semiconductors

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