Physical Verification Engineer (Staff / Sr. Staff)

VelauraHSR Layout, BangalorePosted 2 months ago

Lead or staff
Full time
8+ years

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About the role

Velaura builds compute technology for cloud, edge and Physical AI applications. This engineer will own physical verification signoff, resolve design violations and implement physical fixes through tape-out.

What you'll do

Own block-level and full-chip physical verification signoff
Triage violations and drive signoff closure through tape-out
Debug verification results using Calibre or ICV
Implement layout and routing changes to resolve violations
Develop automation and verification flows for signoff
Mentor engineers on physical verification and tape-out practices

Skills

Must have

Physical verification
Design rule checking
Layout versus schematic
Reliability verification
Advanced-node verification
Physical implementation
Engineering change orders
Tcl
Python
Perl

Nice to have

Esd verification
Eos verification
Latch-up verification
Dfm
Dfy
Metal-fill verification
Foundry rule-deck qualification

Tools

Siemens calibre
Synopsys icv
Cadence innovus
Synopsys fusion compiler
Cadence virtuoso

Who it's for

Education: Engineering degree
Degree: electrical engineering, electronics engineering, vlsi, microelectronics
Experience: 8+ years
Domain: ai semiconductors