Senior CAD Engineer – Physical Design Signoff

Intel develops advanced CPU and SoC designs and their supporting signoff technologies. This engineer will automate physical design signoff flows, resolve signoff issues, and improve methodologies and reporting.

• Develop automation solutions for extraction, timing, ERC, and power signoff
• Build scalable frameworks, scripts, and tools for signoff checks and reporting
• Analyze and resolve timing, extraction, ERC, and power signoff issues
• Improve signoff convergence, quality, and correlation across implementation stages
• Evaluate and deploy signoff capabilities with EDA vendors and CAD teams
• Build dashboards to monitor signoff health and project readiness

Education

Master's degree

Degree

electrical engineering, vlsi, computer engineering

Experience

8+ years

Domain

semiconductors

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