Senior PD Engineer: Synthesis & STA
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About the role
EnCharge AI develops AI hardware. This engineer will own synthesis and signoff for ASIC/SoC blocks, optimize timing and netlists, and collaborate with RTL and physical design teams.
What you'll do
- Own logic synthesis for designated blocks and sub-chips
- Run synthesis quality checks and prepare signoff
- Analyze timing paths and optimize logic depth
- Recommend RTL and micro-architecture changes to improve netlists
- Collaborate with RTL and physical design teams on timing convergence
- Participate in place-and-route execution and full-chip timing convergence
Skills
Must have
- Logic synthesis
- Static timing analysis
- Timing constraints
- Verilog
- Systemverilog
- Digital logic design
- RTL linting
- Clock domain crossing
- Netlist optimization
- Tcl
Nice to have
- Place and route
- Formal verification
- Logic equivalence checking
- Python
- Perl
Tools
- Cadence genus
- Tempus
- Primetime
- Innovus
- Icc2
- Formality
Who it's for
- Experience
- 5 to 8 years
- Domain
- ai hardware
About EnCharge AI
EnCharge AI has 5 open roles in Bangalore, at EnCharge AI India, The Hive at VR Bengaluru. See every EnCharge AI role.
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