STA / Synthesis Engineer (Staff / Sr. Staff / Principal)

Velaura is building compute technology for cloud, edge, and Physical AI applications. You will lead synthesis, static timing analysis, timing closure, and sign-off for advanced compute and AI silicon designs.

• Drive RTL-to-gate synthesis for complex compute and AI designs
• Own timing analysis, constraints, and closure across blocks and chip interfaces
• Optimize designs for timing, power, area, and cost
• Develop and maintain timing constraints and ECO flows
• Automate synthesis, STA, reporting, and debug workflows

Experience

5 to 15 years

Domain

ai semiconductors

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