Staff Engineer, Physical Design - High Speed Interconnects

SiFive develops RISC-V compute platforms and semiconductor IP for applications including data centers, AI, automotive and mobile. This engineer will implement high-speed NoC and Uncore subsystems and optimize their physical design, timing and PPA.

• Execute RTL-to-GDSII physical design for NoC and Uncore subsystems
• Partner with architecture and RTL teams on feasibility and design changes
• Own hierarchical partitioning, macro placement and routing strategies
• Resolve interconnect wire, repeater and clock distribution challenges
• Develop automated hierarchical implementation flows
• Guide engineers and lead design reviews

Education

Engineering degree

Degree

electrical engineering, computer engineering

Experience

7+ years

Domain

semiconductor chip design

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