ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore
CiscoOuter Ring Road, BangalorePosted 25 days agoA free account shows the apply link for every role and matches you to the ones that fit your resume.
About the role
Cisco's Common Hardware Group develops silicon and hardware platforms for networking products, including Cisco Silicon One chips. This technical lead will drive ASIC design-for-test requirements and processes through implementation, signoff and post-silicon validation.
What you'll do
- Define DFT requirements with RTL and physical design teams
- Drive DFT and quality processes across implementation and post-silicon validation
- Develop reusable code and verification strategies
- Coordinate DFT integration into physical design and verification flows
- Debug post-silicon issues and validate test patterns with ATE engineers
- Support physical design signoff and timing closure
Skills
Must have
- Design-for-test
- Jtag
- Scan insertion
- Memory bist
- Boundary scan
- Atpg
- Static timing analysis
- Timing closure
- Gate-level simulation
- Post-silicon validation
Nice to have
- Verilog
- Functional verification
- Dft CAD development
Tools
- Testmax
- Tetramax
- Tessent
- Vcs
Who it's for
- Education
- Engineering degree
- Degree
- electrical engineering, computer engineering
- Experience
- 12+ years
- Domain
- networking hardware
About Cisco
Cisco has 173 open roles in Bangalore, at Cisco Bangalore Campus (Cessna Business Park). See every Cisco role.
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