ASIC DFT Technical Leader || MBIST, SCAN , ATPG, Testmax, Tessent, Post Silicon Validation || Expereince - 11+ years
CiscoOuter Ring Road, BangalorePosted 14 days agoA free account shows the apply link for every role and matches you to the ones that fit your resume.
About the role
Cisco's Common Hardware Group develops silicon and hardware platforms for networking products, including Cisco Silicon One chips. You will lead design-for-test work across ASIC implementation, collaborate on chip design and physical design flows, and support post-silicon validation.
What you'll do
- Define ASIC DFT architecture and requirements early in the design cycle
- Coordinate DFT integration with physical design and verification flows
- Develop reusable DFT code and testing infrastructure
- Drive DFT methodology from design conception through production
- Support post-silicon validation and debug with ATE engineers
Skills
Must have
- Jtag
- Scan insertion
- Atpg
- Static timing analysis
- Timing closure
- Gate-level simulation
- Post-silicon validation
- Silicon debug
- Tcl
- Python
Nice to have
- Verilog
- Functional verification
- Dft CAD development
Tools
- Testmax
- Tetramax
- Tessent
- Vcs
Who it's for
- Education
- Engineering degree
- Degree
- electrical engineering, computer engineering
- Experience
- 12+ years
- Domain
- networking hardware
About Cisco
Cisco has 173 open roles in Bangalore, at Cisco Bangalore Campus (Cessna Business Park). See every Cisco role.
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