DDR Memory Interface System Validation Lead Engineer

Altera develops FPGA technologies for markets including AI, cloud, networking, and edge. You will validate and debug DDR5 and LPDDR5 memory interfaces across FPGA devices and platforms.

• Define and execute validation strategies for DDR5 and LPDDR5 subsystems
• Develop system-level validation environments, test suites, and automation flows
• Perform pre-silicon and post-silicon functional and electrical validation
• Characterize timing, signal integrity, compliance, interoperability, and performance
• Debug memory subsystem issues across silicon, firmware, boards, and systems
• Review memory channel implementations, schematics, layouts, and design guidelines

Education

Engineering degree

Degree

electrical engineering, computer engineering, electronics engineering

Experience

8+ years

Domain

fpga semiconductors

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