Lead Design Engineer ( Synthesis/LEC/CLP )

Cadence develops electronic design software, hardware, and IP for products ranging from chips to complete systems. The engineer will execute and debug synthesis, LEC, and CLP flows and maintain constraints and ECO scripts for ASIC and SoC designs.

• Run and debug LEC sign-off on design blocks
• Improve Genus synthesis QoR and troubleshoot constraints
• Support CLP flows and contribute to sign-off
• Write and maintain ECO scripts and timing and power constraints
• Triage issues and collaborate with PD, DFT, and RTL teams

Education

Engineering degree

Degree

electrical engineering, electronic engineering

Experience

5 to 8 years

Domain

semiconductor design

Cadence Design Systems has 27 open roles in Bangalore, at Cadence Bengaluru, RMZ EcoWorld. See every Cadence Design Systems role.