Senior IP Verification Engineer(IOMMU-N)

SiFive develops RISC-V compute platforms for applications including AI, automotive, data centers, mobile and consumer devices. This engineer will verify IP by developing test plans, UVM testbenches, constrained-random tests and coverage metrics.

• Analyze architecture specifications and create verification test plans
• Develop reusable SystemVerilog and UVM testbenches
• Write constrained-random sequences and tests for corner cases
• Debug RTL and testbench failures using waveform viewers
• Define and track functional and code coverage

Education

Engineering degree

Degree

engineering

Experience

3+ years

Domain

semiconductors

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