Sr Principal Software Engineer

Cadence develops electronic design automation software for technology and chip design. You will debug customer issues and develop or optimize RTL and synthesis features for timing, area and power.

• Analyze and debug customer problems in applications and products
• Develop features and enhancements to improve synthesis results
• Write, update and optimize RTL code in VHDL or Verilog
• Run functional simulations, timing analysis and design-for-test checks
• Investigate simulator performance and accuracy issues

Education

Engineering degree

Degree

computer science

Experience

12 to 16 years

Domain

eda software

Cadence Design Systems has 27 open roles in Bangalore, at Cadence Bengaluru, RMZ EcoWorld. See every Cadence Design Systems role.