Staff Engineer, ASIC IP STA

Micron develops DRAM, NAND, and NOR memory and storage products. This engineer will perform post-layout static timing signoff and close timing for high-speed interface IPs, supporting their integration into SoCs.

• Perform post-layout static timing analysis and signoff for high-speed interface IPs
• Drive timing closure across IP development and SoC integration
• Develop, validate, and debug timing constraints and timing models
• Generate and validate SDF and support gate-level simulation
• Automate timing analysis and signoff workflows using TCL or Python

Education

Engineering degree

Degree

electrical engineering, electronics, vlsi

Experience

6 to 10 years

Domain

semiconductor memory

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