DFT Engineer

Astera Labs provides semiconductor connectivity solutions and software for rack-scale AI infrastructure. This engineer will design and implement RTL blocks, collaborate across silicon teams, and help deliver designs from specifications through tapeout.

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
• Develop synthesizable Verilog and SystemVerilog with attention to PPA
• Drive design reviews, lint, CDC, and timing closure
• Partner with architecture, verification, DFT, and physical design teams
• Debug pre-silicon and post-silicon issues across design environments

Education

Engineering degree

Degree

electrical engineering, computer engineering

Experience

5+ years

Domain

ai infrastructure semiconductors

Astera Labs has 11 open roles in Bangalore, at Astera Labs Bengaluru, Helios Business Park. See every Astera Labs role.