Tech Lead– Verification Methodology/CAD

Astera Labs develops semiconductor connectivity solutions and software for rack-scale AI infrastructure. You will build verification automation and infrastructure, improve verification workflows, and guide methodology adoption across engineering teams.

• Own verification methodology and infrastructure across projects
• Build frameworks for simulation, regression, coverage, debug and signoff
• Automate verification workflows using scripting languages and tools
• Integrate EDA and verification tools into common workflows
• Improve regression speed through parallelization and optimization
• Mentor verification engineers and establish reusable methodology standards

Education

Engineering degree

Degree

electronics, electrical engineering, computer science, computer engineering, vlsi

Experience

6 to 12 years

Domain

ai infrastructure semiconductors

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