Principal Design Verification Engineer
Astera LabsBellandur, BangalorePosted 2 months agoA free account shows the apply link for every role and matches you to the ones that fit your resume.
About the role
Astera Labs provides rack-scale AI infrastructure through semiconductor connectivity solutions and software. This engineer will plan and execute functional verification of PCIe and CXL designs, develop test sequences and assertions, and analyze coverage.
What you'll do
- Develop block-level and system-level verification plans
- Write and execute test sequences and close coverage
- Debug failures with RTL designers
- Develop randomized constraints for transaction-based verification
- Write assertions and analyze coverage data
- Create VIP abstraction layers for scalable verification
Skills
Must have
- Functional verification
- Pci express
- Cxl
- Uvm
- Assertions
- Coverage analysis
- Verification planning
- Test sequence development
Nice to have
- Physical layer verification
- Link layer verification
- Transaction layer verification
- Noc
- Qos
- Switching fabric performance analysis
Who it's for
- Education
- Engineering degree
- Degree
- electrical engineering, computer engineering
- Experience
- 12+ years
- Domain
- ai infrastructure
About Astera Labs
Astera Labs has 11 open roles in Bangalore, at Astera Labs Bengaluru, Helios Business Park. See every Astera Labs role.
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