Lead Logic Design Engineer
Astera LabsBellandur, BangalorePosted a month agoA free account shows the apply link for every role and matches you to the ones that fit your resume.
About the role
Astera Labs develops semiconductor connectivity solutions and software for rack-scale AI infrastructure. You will lead architecture and RTL development for connectivity IP, supporting integration, optimization, verification, and silicon debug.
What you'll do
- Lead RTL and microarchitecture development for connectivity IP and subsystems
- Translate specifications into hardware architecture and scalable logic
- Optimize performance, latency, area, and power
- Collaborate with verification, SoC integration, and physical design teams
- Support post-silicon debug and root-cause analysis
Skills
Must have
- RTL design
- Systemverilog
- Verilog
- Pcie architecture
- Connectivity ip design
- Microarchitecture
- Digital logic design
- Flow control
- Arbitration
- Error handling
Nice to have
- Switching silicon
- Silicon production
Who it's for
- Experience
- 6 to 10 years
- Domain
- ai infrastructure semiconductors
About Astera Labs
Astera Labs has 11 open roles in Bangalore, at Astera Labs Bengaluru, Helios Business Park. See every Astera Labs role.
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