Principal Logic Design Engineer
Astera LabsBellandur, BangalorePosted a month agoA free account shows the apply link for every role and matches you to the ones that fit your resume.
About the role
Astera Labs provides semiconductor connectivity solutions and software for rack-scale AI infrastructure. This engineer will lead architecture and RTL design for connectivity IP and subsystems through integration and silicon bring-up.
What you'll do
- Lead RTL and microarchitecture development for connectivity IP and subsystems
- Translate specifications and system requirements into hardware architecture
- Design and optimize high-performance logic for controllers and subsystems
- Collaborate with verification, SoC integration, and physical design teams
- Lead technical reviews and mentor senior engineers
- Support post-silicon debugging and root-cause analysis
Skills
Must have
- RTL design
- Systemverilog
- Verilog
- Pcie architecture
- Connectivity ip design
- Microarchitecture
- Flow control
- Arbitration
- Error handling
- Debugging
Nice to have
- Switching silicon
- Silicon production
Who it's for
- Experience
- 10+ years
- Domain
- ai infrastructure semiconductors
About Astera Labs
Astera Labs has 11 open roles in Bangalore, at Astera Labs Bengaluru, Helios Business Park. See every Astera Labs role.
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