Tech Lead, Formal Verification

Astera Labs provides semiconductor connectivity solutions and software for AI infrastructure. This engineer will lead formal verification for complex IP and SoC designs, develop verification environments, and guide verification methodologies across projects.

• Develop formal verification plans from architecture and design specifications
• Create and execute formal environments, assertions, properties, and checkers
• Drive proof convergence using abstraction and complexity reduction techniques
• Evaluate and scale verification methodologies, flows, and tools
• Mentor engineers and lead bug triage and root-cause analysis
• Estimate verification effort, track progress, and support sign-off strategies

Education

Engineering degree

Degree

electronics, electrical engineering, computer engineering

Experience

5 to 10 years

Domain

ai infrastructure semiconductors

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